5.2 Sample and Hold

The purpose of the sample and hold circuitry is to take a snapshot of the sensor signal and hold the value. The ADC must have a stable signal in order to accurately perform a conversion. An equivalent circuit for the sample and hold is shown in Figure 44. The switch connects the capacitor to the signal conditioning circuit once every sample period. The capacitor then holds the voltage value measured until a new sample is acquired. Many times, the sample and hold circuitry is incorporated into the same integrated circuit package.

  

Figure 44: Equivalent Circuit for a Sample and Hold

5.2.1 Problems with a Sample and Hold:

1. Finite Aperture Time: The sample and hold takes a period of time to capture a sample of the sensor signal. This is called the aperture time. Since the signal will vary during this time, the sampled signal can be slightly off.
2. Signal Feedthrough: When the sample and hold is not connected to the signal, the value being held should remain constant. Unfortunately, some signal does bleed through the switch to the capacitor, causing the voltage being held to change slightly.
3. Signal Droop: The voltage being held on the capacitor starts to slowly decrease over time if the signal is not sampled often enough.

5.2.2 Solution

The main solution to these problems is to have a small aperture time relative to the sampling period. This means that if the HCI designer uses a high sampling rate, the aperture time of the sample and hold must be quite small.